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DSDAC 1.0 (standard model / Super clock model)
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DSDAC 1.0 (standard model / Super clock model)

. DSDAC1.0 is a high-performance audio DAC based on DSD theory. It is completely different from ordinary DAC because it has many original technologies. It does not use conventional chips for DA conversion but FPGA and discrete components for digital processing . . DSDAC1.0 can increase the frequency of all input data including PCM or dsd64 to dsd1024. If the input data is higher than the dsd128, you can also output it directly without increasing. DSD frequency raising algorithm is a very complex mathematical process, DSDAC1.0 did a good job. . One year after the standard model was launched,the super clock model was launched. Performance is futher improved
Number of views:
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DAC
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Product description

 

       DSDAC1.0 is an audio DAC based on DSD audio technology.  It took five years to develop and realized  the perfect playback of DSD audio.  It has three advanced audio technologies.

 

    1: high-precision DSD frequency up algorithm,

    2: synchronous direct clock,

    3: clock blocking technology. 


        It is a perfect DSD audio DAC.  DSDAC1.0 has three models : standerd, super clock model , deluxe model.

 

Difference between DSDAC1.0 standerd model and super clock model  

 

1: The clock system of  super clock model has higher performance, RMS jitter is as low as 100fs

2: Some advance component are used

 

 


 

1、 R & D background
 

      DSD audio coding mode is  almost perfect although it has many technical barriers.  The unique charm of  DSD sound  attracts many people,  many music lovers have high enthusiasm for DSD in the past decade.  At present more than 10000 SACD music albums have been released in the world  which is a valuable music resource for mankind.  In order to make it play a greater role many people are making unremitting efforts  and we are one of them.
 

      Due to the disc storage space is limited,  SACD adopts the dsd64 format which with lower frequency.  The accuracy of dsd64 in DA conversion is low and there is out of band noise (noise above 23khz) after  DA process.  Therefore, most SACD players must convert dsd64 to PCM  before DA conversion. This way weakens the advantages of DSD , and it was an important reason why SACD fails in the competition with CD.

 

       With the passage of time ,  more in-depth research on DSD coding technology have made progress.  FPGA technology has also made great progress.  Therefore the technology of raise DSD frequency form 2.8224MHz to high number has been available.  It can make the DA process with higher accuracy after frequency  was rised .  At the same time because the frequency of out of  band noise is pushed up , it can be easily filtered out.  Based on these conditions we decided to start the research and development the algorithm for DSD frequency  increasing .
 
 
 

 
2、 R & D history

 

       DSD technology is a commercial technology,  so there is little public information can be found.   After several years of efforts , we studied the basic theory of DSD and created a unique algorithm to realize the high-precision frequency rising.  At the same time  we made a comprehensive innovation in the clock  framework ,  created two unique technologies of "synchronous direct clock" and "clock blocking". 
 

      Analog circuit is the key part of DAC. The advantages of the digital part must rely on the analog circuit . One deviation of the analog part is enough to offset the three advantages of the digital part.  The R & D team of DSDAC1.0 spent nearly a year for designing the circuit architecture of the analog part more than 20 times.   After a long period of adjustment ,dsdac1.0 has reached the level of reference DAC
 

 


 
3、 Core technology
 

       The high-precision frequency rise algorithm  is the core of  DSDAC1.0.   Although there are many ways to realize frequency rising  but the high-precision frequency rise  algorithm is a complex mathematical problem  not a digital technical problem.  The technology of frequency rising not only makes DSD more widely used but also makes DSDAC1.0 become leading audio DAC.
 

       Synchronous direct clock technology :  femtosecond clock inside DSDAC1.0 will be sent to the shift register directly without any intermediate conversion , so that the performance of femtosecond clock is directly reflected in the analog output.  This technology is different from the use of external femtosecond clock and built-in femtosecond crystal oscillator.  The use of external clock and built-in crystal oscillator can only be a source clock,  it must be divided by frequency divider.  In this way,  there are large additive jitter which changes the femtosecond clock from femtosecond to picosecond.  The clock of DSDAC1.0 can be sent to shift register directly  without frequency divider,  it is advanced technology of clock application .

 

       Clock blocking.   It means that the clock from the pre-devices is abandoned and the DSDAC1.0 only uses the local clock.  In this way, the clock of pre-devices such as digital turntable, CD player and digital interface will no longer affect the performance of  DAC.  As long as the data is correct,  there is no difference in any digital source.  This technology is a dream of digital audio.  Clock blocking  is  synchronization process,  not the ASRC , which has great negative impact on sound quality.  It solves the clock problem that has plagued the digital audio field for a long time.
 
 
        DSDAC1.0 has advanced USB interface and can receives DSD source code in native mode.  As a DSD DAC ,  receives DSD source code is a necessary function.  DSDAC1.0 has two ways to input DSD source code:  one is to input dsd64 via SPDIF in DOP mode ,  and the other is to input dsd512 via USB in native mode.  The XU208 scheme of XMOS inside DSDAC1.0 has ground isolation function ,  the interference of the front digital source can be almost  isolate.  We have customized the special driver from XMOS to enable DSDAC1.0 to receive the source code of dsd512 in native mode.

 

 

 


Functional parameters


 
SPDIF sampling rate:   PCM 192 kHz / dop64 (AES, optical fiber, coaxial, BNC )
 
USB sampling rate:   pcm384 / dsd512 (native)
 
Output interface:   one for XLR and one for RCA
 
Output level:   5.0V RMS (XLR), 2.5V RMS (RCA)
 
Volume control range:   - 70dB ~ 0dB
 
Overall dimension:   430 * 360 * 100mm
 
Net weight:  10.6kg
 
Gross weight:  13.3kg

 

 

 

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